tag:blogger.com,1999:blog-4503292949532760618.post1022628543285485005..comments2024-03-28T13:39:27.601-07:00Comments on DSHR's Blog: A Challenge to the Storage IndustryDavid.http://www.blogger.com/profile/14498131502038331594noreply@blogger.comBlogger1125tag:blogger.com,1999:blog-4503292949532760618.post-83243394938656449982014-09-23T13:02:46.214-07:002014-09-23T13:02:46.214-07:00In the discussion Dave Anderson pointed to proof t...In the discussion Dave Anderson pointed to proof that Seagate, at least, is thinking along these lines. In a 2013 paper entitled <a href="http://ieee-hpec.org/2013/index_htm_files/8-Exploiting-free-li-gomez-lilja-2873673.pdf" rel="nofollow"><i>Exploiting Free Silicon for Energy-Efficient Computing Directly in NAND Flash-based Solid-State Storage Systems</i>,</a>, Peng Li and Kevin Gomez of Seagate and David Lilja of the Univ. of MN describe their concept of the Storage Processing Unit (SPU). This involves integrating a low-power CPU with the flash memory, which is what DAWN would require, and matches what <a href="http://blog.dshr.org/2014/01/implementing-dawn.html%22" rel="nofollow">Bunnie Huang found</a>. They come to the same conclusion that, with very different hardware, FAWN did:<br /><br />"Simulation results show that the SPU-based system is at least 100 times more energy-efficient than the conventional system for data-intensive applications."<br /><br />The interesting part is why they believe the SPU is made of "free silicon". To understand this, you need to understand the chip design concept of "pad-limited". The pads of a chip are where the wires that transmit power and signals attach to the silicon, and their size is fixed by the process of bonding the wires to the silicon. Normally, the pads are arranged around the periphery of the chip, so the number of pads and their size determine the circumference of the chip. This means that a chip with a given number of connections has to have at least a certain area, whether or not it needs that area to implement the functions of the chip. A chip that needs less area to implement its functions than is enforced by its pads is called pad-limited. The chip area "wasted" can be used to implement other functions and is thus effectively free.<br /><br />It turns out that flash vendors are already using some of this free silicon:<br /><br />"For example, both the Micron ClearNAND and the Toshiba embedded multi-media card (eMMC) have integrated the hardware ECC into a die inside the NAND flash package. In addition, since the die area is pad-limited, manufacturers like Micron and Toshiba also have integrated a general purpose processor into the die to implement parts of the FTL [Flash Translation Layer] functions, such as block management, to further increase the SSD performance."<br /><br />"In fact, even with the integrated general purpose processor and the hardware ECC, the die still has available area. Thus, we can integrate more logic units without any additional cost."David.https://www.blogger.com/profile/14498131502038331594noreply@blogger.com